ATG Press Appetizer

Although our major research program (Orange Program) is to form the foundation of non-traditional computer science, we have established Appetizer Program to make some possible adjustments in the traditional computer science. These moderate adjustments are expected to foster some substantial improvements in the computer industry. In spite of the Orange Program that requires very deep and new works in philosophy and physics, the Appetizer Program does not need such backgrounds. The only requirement in our Appetizer Program is organized thinking.

Each year, we work on one project (say Appetizer) and publish its electronic version on 21st day in December of that year. Four sequential Appetizers make a volume, which is published in both electronic and paper-based formats. Since the first Appetizer is published in 2000, the first volume of it will be available in December 2003. All of the Appetizers are free materials.

Our major goal of publishing this sequence of free papers is to present some promising and critical ideas for the future of computer industry to all of the active players in the field. We hope these ideas motivate and inspire the major players in the field to develop more creative solutions in the future. This is why we refer to this program as appetizer. The minimum expected benefit of this program is to give the academic and industrial firms around the world a better outlook in their future research and development policies and activities.

The following is the list and the PDF version of articles in ATG Press Appetizer, Volume I . You can also download the whole volume I PDF version (403 KB).

1. Globe CPU; (scheduled publication date: December 21, 2000; publication delay: less than 1 month)

Abstract:
Current microprocessor architecture suffers from employing some invented traditions in the 60s. Adhering those traditions has originated many unjustifiable design-level complexities till now. Many approaches that are based on those traditions have come to dead end in recent years. Among them, pipelining and superscalar techniques are notable. In this paper, we show that a powerful microprocessor does not need pipelining and superscalar techniques. The natural result of such an approach, which we call it globe scale architecture is the removal of branch prediction, speculative execution, and very long instruction words. Finally, we conclude that a typical CPU based on the proposed architecture dose not need more than the one-tenth of the transistors placed in a typical year-2000 microprocessor. In addition, it is shown that the proposed architecture achieves the best running speed for a sequential computer program.

Abstract
The popularity of a technology does not always help to its improvement. Among different technologies, application server is a good example. The Internet boom of the 1990s absorbed many attentions and resources to the development of more advanced application servers, which are the building blocks of the modern Internet. Since most servers on the Internet are information centric (versus computation centric), the result of those developments has been a big generation of standards for data and information representation. The standards by themselves, cannot improve the core technologies of application servers, either information or computation centric. In this paper, we present a software architecture for a typical application server which covers both information and computation centric paradigms. We call it globe server and the goal of this architecture is the improvement of application server core technology. It is a quite different concept from the standards for data and information representation.

Abstract
Current application client technologies (both of thin and rich) are immature when compared to application server technologies. The immaturity is originated in different technical and commercial issues. Technically, application clients have not strong and universal definitions and standards (e.g. something like HTML) as application servers have. Commercially, business sector represents itself through its application servers, so the development efforts are diverted to the server-side projects. From the engineering point of view, since the overall performance on a network depends on both of client and server, the client-side developments are as important as the server sides. In this paper, we try to categorize technically plausible application clients into a few comprehensive classes and put a definition upon each class. Afterward, we show a way in which each class can be standardized for the future coherent developments. Finally, we highlight the classes that have a remarkable potential for the current and the future commercial applications.

Abstract
The field of combinatorial optimization and integer programming has a rich literature but a poor progress. It is due to the limited number of fundamental concepts which are applicable in the development of the field, so the major research efforts go through the different combinations of these concepts to reach for a slightly better result. Since it has been proved that most problems in this field are in NP-C class, almost all of the efforts are diverted to finding good approximating methods to the solution of these problems. A few heuristic methods from the older greedy approaches to the newer genetic algorithms are the engines of these approximations. There are also a few exact methods like the dynamic programming and the branch and bound, which have a quite narrow applicability. In this paper, we introduce a new original method to the solution of combinatorial optimization problems, which is called coordinated brute force method. Basically, It is an exact method to the solution of NP-C problems, but it can be converted into a record breaking approximating method by a few slight changes. We apply this method to three famous NP-C problems: the traveling salesman as the hardest NP-C, the facility location as a strong NP-C, and the knapsack as a non-strong NP-C.

The following is the list and the PDF version of articles in ATG Press Appetizer, Volume II . We have not any Appetizer in 2004, so the start of the new series is December 2005.

1. Information Architecture I: Ultimate CPU Architecture
(scheduled publication date: December 21, 2005)

2. Information Architecture II: Data & Component Architecture
(scheduled publication date: December 21, 2006)

3. Information Architecture III: Data & Component Coordination
(scheduled publication date: December 21, 2007)

4. Information Architecture IV: Natural Language Architecture
(scheduled publication date: December 21, 2008)

You can also get some information about our unscheduled publications by visiting our scratchpad.